1. Field of the Invention
The present invention relates generally to an output circuit in a semiconductor device, and in particular to an output circuit capable of improving the load driving performance of the semiconductor device.
2. Description of the Related Art
To improve the speed and the integration of elements in a semiconductor device, such as a semiconductor integrated circuit, the supply voltage needed by the integrated circuit should be as low as practical and the integrated circuit should have a low level output impedance. The semiconductor integrated circuit has an internal circuit and an output circuit. The output circuit receives a signal processed by the internal circuit and outputs a high or low level output signal to an external bus based on the power supplied from the power supply.
A host computer is connected to individual terminals via lines, forming a LAN (Local Area Network). Even if the power supply to the individual terminals is cut off to deactivate those terminals, the lines of the LAN are enabled high. When the lines are enabled high and power supply is stopped, the output circuit used in a terminal in the network should be set to a high impedance state. However, if the output circuit has a pull-up P channel MOS transistor and a pull-down N channel MOS transistor connected in series between a high-potential power supply and a low-potential power supply, the output circuit can not be set to a high impedance state. The reason for this is that the P channel MOS transistor incorporates a parasitic diode which prevents the output signal from being set to a high impedance state even if the power supply is blocked. In this respect, the output circuit used as a terminal in a LAN normally has a bipolar transistor or an N channel MOS transistor. The output circuit uses those transistors for the pull-up and pull-down transistors.
FIG. 1 shows a first example of a conventional output circuit 101. The output circuit 101 comprises an inverter circuit 1a, a pull-up first N channel MOS transistor Tr1 and a pull-down second N channel MOS transistor Tr2. The inverter circuit 1a is connected between an input terminal Ti and the gate of the first N channel MOS transistor Tr1. The inverter circuit 1a outputs an inverted signal of an input signal IN as an input signal /IN to the gate of the first N channel MOS transistor Tr1. The second N channel MOS transistor Tr2 has a gate connected to the input terminal Ti with the input signal IN input to the gate. The first transistor Tr1 has a drain connected to a power supply V.sub.CC and a source connected to an output terminal To. The second transistor Tr2 has a drain connected to the output terminal To and a source connected to a ground GND as a low-potential supply.
With the supply voltage V.sub.CC supplied to this output circuit 101, when the input signal IN goes high, the inverter circuit 1a outputs a low level input signal /IN to the gate of the first transistor Tr1, turning off the first transistor Tr1. In response to the high input signal IN, the second transistor Tr2 turns on. The output circuit 101 then generates a low level output signal OUT from the output terminal To.
When the input signal IN goes low, the inverter circuit 1a outputs signal /IN high to the first transistor Tr1, turning the first transistor Tr1 on. In response to the low input signal IN, the second transistor Tr2 turns off. Then, the output circuit 101 outputs a high level output signal OUT from the output terminal To.
When power supply to the semiconductor integrated circuit including this output circuit 101 is cut off, the transistors Tr1 and Tr2 both turn off and the output circuit 101 is set to a high impedance state. Should a LAN connection (not shown) to the output terminal To be enabled high, the gate potentials of the first and second transistors Tr1 and Tr2 would be low enough to keep the output circuit 100 off. As a result, the parasitic diodes in the first and second transistors Tr1 and Tr2 will not operate.
When signal OUT is output high from the terminal To, the output circuit 101 provides the signal OUT at a level lower than the supply voltage V.sub.CC, the difference being the threshold value of the first transistor Tr1. Therefore, should the output circuit 101 assert the signal OUT high, the circuit 101 will not have sufficient power to drive a load connected via the LAN connection.
FIG. 2 shows a second example of the conventional output circuit 102. The output circuit 102 comprises an inverter circuit 1b, first and second N channel MOS transistors Tr3 and Tr4, a booster circuit 2, which includes a transistor and a capacitor, and a voltage converter 3. The booster circuit 2 boosts the supply voltage V.sub.CC to a predetermined voltage in response to a received clock signal CLK. The booster circuit 2 produces an output voltage V.sub.CC H by boosting the supply voltage V.sub.CC of, for example, 5 V to about 10 V, and then outputs the output voltage V.sub.CC H to the voltage converter 3. The inverter circuit 1b inverts the input signal IN and supplies it as input /IN to the voltage converter 3. The second transistor Tr4 receives the input signal IN from its gate. In response to the high input signal IN, the voltage converter 3 outputs the output voltage V.sub.CC H from the booster circuit 2 to the gate of the first transistor Tr3. In response to the low input signal /IN, the voltage converter 3 outputs a low signal equivalent to the ground GND to the gate of the first transistor Tr3. The first transistor Tr3 has a drain connected to the power supply V.sub.CC and a source connected to the output terminal To. The second transistor Tr4 has a drain connected to the output terminal To and a source connected to the ground GND.
With the supply voltage V.sub.CC supplied to this output circuit 102, when the input signal IN goes high, the inverter circuit 1b outputs a low level input signal /IN to the gate of the first transistor Tr3 in response to that input signal IN. This turns the first transistor Tr3 off. In response to the high input signal IN, the second transistor Tr4 is turned on. The output circuit 102 then outputs the low output signal OUT from the output terminal To.
When the input signal IN goes low and the input signal /IN goes high, the voltage converter 3 outputs the output voltage V.sub.CC H provided by the booster circuit 2 to the gate of the first transistor Tr3. The first transistor Tr3 turns on in response to the output voltage V.sub.CC H, and the second transistor Tr4 turns off in response to the low input signal IN. The output circuit 102 can then output the signal OUT at a level equivalent to the level of the supply voltage V.sub.CC. This allows the output circuit 102 to have an improved load driving performance when compared with the output circuit 101 of the first example. When power supply to the output circuit 102 in the second example is cut off, the transistors Tr3 and Tr4 both turn off and the output circuit 102 is set to a high impedance state, as per the first example.
The output circuit 102 of the second example however requires the booster circuit 2 which normally operates in accordance with the supplied supply voltage V.sub.CC and clock signal CLK. The operation of this booster circuit 2 increases the consumed power of the output circuit 102. This output circuit 102 also requires the voltage converter 3. This requirement results in an increase to the size of the output circuit 102.